A System Level Resource Estimation Tool for FPGAs

High level modeling tools make it possible to synthesize a high performance FPGA design directly from a Simulink model. Accurate estimates of the FPGA resources required provides the system designer important feedback on area and cost, which is valuable even during early design iterations. Previous approaches to hardware resource estimation suffer a combination of inaccuracy, slowness, and/or high complexity, which limits their practicality at the algorithm definition stage. We address these restrictions with a fast resource estimation tool incorporated in the Xilinx System Generator. Implemented using MATLAB code, the estimator run time is proportional to the Simulink compilation time, and typically takes from seconds to minutes depending upon the size of the Simulink model. Estimates are conservative, and accurate to within 10% of the post-mapping implementation report. In this paper, we explain how block resource information is characterized in a MATLAB function. This characterization also estimates logic that will be trimmed during synthesis and mapping. Finally, we describe how these estimation functions are integrated within Simulink in a user-friendly and automated infrastructure. This approach has been incorporated in System Generator since version 3.1.